1. Field of the Invention
The present invention relates to complimentary metal oxide semiconductor (CMOS) devices and, in particular, to a technique for eliminating impact ionization in high density CMOS circuit configurations allowing higher supply levels and, thus, larger dynamic range.
2. Background of the Invention
While the advancement of CMOS technology has resulted in high density processes, a major limitation on the technology has been the allowable drain-to-source voltage (V.sub.ds) for N-type MOS transistors. The limitation, typically five volts, is due to shallow/sharp junctions and thin gate oxides. These factors result in impact ionization. Thus reliability problems occur in sub-micron processes due to impact ionization during positive five volt to negative five volt switching transients.
Many mixed analog/digital integrated circuits require logic low levels of both zero volts and negative five volts for interfacing purposes. Thus implementation of logic to meet this requirement results in impact ionization problems for sub-micron processes. Impact ionization is a phenomenon that occurs primarily in n-channel MOS devices rather than p-channel because the electron mobility in n-channel devices is higher than the hole mobility of p-channel devices. When the supply voltage is increased above five volts to the point where the allowable V.sub.ds of the device is exceeded, electron mobility is such that collisions occur at the drain. These collisions ionize the semiconductor crystal and create electron/hole pairs. As illustrated in FIGS. 1A-C, when this occurs, the drain-to-substrate current increases above the normal leakage to contribute to the total drain current. This causes a slow but permanent threshold shift which results in device failure over a period of time. Additionally, it reduces the output impedance for saturated device applications.
It is known to us lightly doped diffusion (LDD) or increased junction depth. Both of these solutions reduce the field in the oxide eliminating the hot carrier effect. However, both solutions complicate the fabrication process and increase n-channel device sizes. Another solution includes use of cascading techniques. However these techniques require special biasing circuitry.
The above stated problems limit supplies to five volts and thus reduce the maximum possible dynamic range for CMOS analog circuits. If this effect can be eliminated, higher dynamic ranges can be achieved. This would permit the higher density CMOS processes required for digital applications to be integrated with high dynamic range CMOS analog circuitry, taking full advantage of the advancements in the technology.
It is know in the art to solve these problems using complicated process steps which increase device size. It is also known to use cascade type circuit techniques requiring special cascode circuitry, complicated back biasing circuits, and bias generator circuits to provide internal bias changes.
Additionally, it is known in the prior art to provide a second MOS device with a fixed gate voltage in series with an MOS device such the V.sub.ds is equally divided across the two devices. This permitted higher voltage swings and preserved high output impedance thereby permitting high gain for an amplifier or high impedance for a current source. Doubling of the dynamic range was possible because the two devices divided the voltage between them. This method is disclosed in U.S. Pat. No. 4,736,117 issued to Wieser issued on Apr. 5, 1988. However the combined devices of Wieser can not be used for applications using both zero volt and negative five volt substrate biasing.